Avnet ASIC Launches Ultra-Low-Power Design Services for TSMC’s Advanced 4 nm Process Technologies

Introduction to Avnet ASIC’s New Design Services

Avnet ASIC, a division of Avnet Silica and an Avnet company, has announced the launch of its new ultra-low-power design services tailored for TSMC’s cutting-edge 4 nm and below process technologies. These services are specifically designed to help customers achieve exceptional power efficiency and performance in high-performance applications such as blockchain and AI edge computing.

Advanced Solutions for Power Efficiency

TSMC, the world’s leading silicon foundry, collaborates with Avnet ASIC, a leading provider of ASIC and SoC full turnkey solutions, to address the challenges associated with operating at extreme low-voltage conditions in the 4 nm and below nodes. The new design services include recharacterizing standard cells for lower voltages, performing early RTL exploration for optimizing power, performance, and area (PPA) tradeoffs, implementing an optimized clock tree, and utilizing transistor-level simulations to enhance the power optimization process.

Comprehensive Technical Approach

The Avnet ASIC team has developed a full-scale technical A-Z approach to enable PPA optimization of high-performance chips working at extremely low voltage. This has been demonstrated and validated in TSMC’s 4 nm process. Performance, dynamic, and leakage power estimations have been confirmed by post-silicon validation. Customers define the board solution and chip implementation concept, requirements, and execute front-end design based on library characterization for near-threshold voltage operation. Avnet ASIC then executes the design to meet aggressive market targets, ensuring ultra-low-power performance for the customer’s application.

Industry Impact and Future Prospects

“One of the industry challenges today is to optimize application performance by choosing the correct technology to meet customer needs,” said Pavel Vilk, GM and Head of Engineering at Avnet ASIC. “TSMC’s 4 nm process provides a great opportunity to save power and area without compromising target performance. However, operating at low voltages requires significant effort on voltage drop optimization through a holistic solution of board-package-chip design.”

The new initiative follows the announcement of Avnet ASIC’s appointment as a Value Chain Aggregator (VCA) by TSMC in February. This collaboration enhances Avnet ASIC’s offerings by combining TSMC’s advanced silicon processes with Avnet ASIC’s design and manufacturing capabilities, enabling access to comprehensive ASIC SoC solutions for customers.